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| Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF51AG128 Rev. 5, 6/2010 MCF51AG128 MCF51AG128 ColdFire Microcontroller Covers: MCF51AG128 and MCF51AG96 The MCF51AG128 is a member of the ColdFire(R) family of 32-bit variable-length reduced instruction set (RISC) microcontroller. This document provides an overview of the MCF51AG128 series MCUs, focusing on its highly integrated and diverse feature set. The MCF51AG128 derivative are low-cost, low-power, and high-performance 32-bit ColdFire V1 microcontroller units (MCUs) designed for industrial and appliance applications. It is an ideal upgrade for designs based on the MC9S08AC128 series of 8-bit microcontrollers. The MCF51AG128 features the following functional units: * 32-bit Version 1 ColdFire(R) central processor unit (CPU) - Up to 50.33 MHz ColdFire CPU from 2.7 V to 5.5 V - Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM (0.76 DMIPS per MHz when running from flash) - Implements Coldfire Instruction Set Revision C (ISA_C) * On-chip memory - Up to 128 KB flash memory read/program/erase over full operating voltage and temperature - Up to 16 KB random access memory (RAM) - Security circuitry to prevent unauthorized access to RAM and flash contents * Power-Saving Modes - Three ultra-low power stop modes and reduced power wait mode - Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents * System Protection - Advanced independent clocked watchdog (WDOG) with features like, robust refresh mechanism, windowed mode, high granulation timeout, fast test of timeout, and always forces a reset - Additional external watchdog monitor (EWM) to help reset external circuits - - - - 80 LQFP 14 mm x 14 mm 64 LQFP 10 mm x 10 mm 48 LQFP 7 mm x 7mm 64 QFP 14 mm x 14 mm Low-voltage detection with reset or interrupt Separate low voltage warning with selectable trip points Illegal opcode and illegal address detection with reset Flash block protection for each array to prevent accidental write/erasure - Hardware CRC module to support fast cyclic redundancy checks * Debug Support - Single-wire back ground debug interface - Real-time debug support, with six hardware breakpoints (4 PC, 1 address pair and 1 data) that can be configured into a 1- or 2-level trigger - On-chip trace buffer provides programmable start/stop recording conditions - Support for real-time program (and optional partial data) trace using the debug visibility bus * DMA Controller - Four independently programmable DMA channels provide the means to directly transfer data between system memory and I/O peripherals - DMA enabled peripherals include IIC, SCI, SPI, FTM, HSCMP, ADC, RTC, and eGPIO, and the DMA request from these peripherals can be configured as DMA source or as an iEvent input * CF1_INTC - Support of 44 peripheral I/O interrupt requests and seven software (one per level) interrupt requests - Fixed association between interrupt request source, level and priority, up to two requests can be remapped to the highest maskable level and priority - Unique vector number for each interrupt source - Support for service routine interrupt acknowledge (software IACK) read cycles for improved system performance - Ability to mask any individual or all interrupt sources Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2010. All rights reserved. * System Clock Sources - Oscillator (XOSC) -- Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz - Internal Clock Source (ICS) -- Frequency-locked-loop (FLL) controlled by internal or external reference; trimmable internal reference allows 0.2% resolution and 2% deviation (1% across 0 to 70 C) * Peripherals - ADC -- 24 analog inputs with 12 bits resolution; output formatted in 12-, 10- or 8-bit right-justified format; single or continuous conversion (automatic return to idle after single conversion); interrupt or DMA request when conversion complete; operation in low-power modes for lower noise operation; asynchronous clock source for lower noise operation; selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent; dual samples based on hardware triggers during ping-pong mode; on-chip temperature sensor - PDB -- 16-bit of resolution with prescaler; seven possible trigger events input; positive transition of trigger event signal initiates the counter; support continuous trigger or single shot, bypass mode; supports two triggered delay outputs or ORed together; pulsed output could be used for HSCMP windowing signal - iEvent -- User programmable combinational boolean output using the four selected iEvent input channels for use as interrupt requests, DMA transfer requests, or hardware triggers - FTM -- Two 6-channel flexible timer/PWM modules with DMA request option; deadtime insertion is available for each complementary channel pair; channels operate as pairs with equal outputs, pairs with complimentary outputs or independent channels (with independent outputs); 16-bit free-running counter; the load of the FTM registers which have write buffer can be synchronized; write protection for critical registers; backwards compatible with TPM - TPM -- 16-bit free-running or modulo up/down count operation; two channels, each channel may be input capture, output compare, or edge-aligned PWM; one interrupt per channel plus terminal count interrupt - CRC -- High speed hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial; error detection for all single, double, odd, and most multi-bit errors; programmable initial seed value - HSCMP -- Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparator output; the positive and negative inputs of the comparator are both driven from 4-to-1 muxes; programmable voltage reference from two internal DACs; support DMA transfer - IIC -- Compatible with IIC bus standard and SMBus version 2 features; up to 100 kbps with maximum bus loading; multi-master operation; software programmable for one of 64 different serial clock frequencies; programmable slave address and glitch input filter; interrupt driven byte-by-byte data transfer; arbitration lost interrupt with automatic mode switching from master to slave; calling address identification interrupt; bus busy detection; broadcast and 10-bit address extension; address matching causes wake-up when MCU is in Stop3 mode; DMA support - SCI -- Two serial communications interface modules with optional 13-bit break; full-duplex, standard non-return-to-zero (NRZ) format; double-buffered transmitter and receiver with separate enables; 13-bit baud rate selection with /32 fractional divide; interrupt-driven or polled operation; hardware parity generation and checking; programmable 8-bit or 9-bit character length; receiver wakeup by idle-line or address-mark; address match feature in receiver to reduce address-mark wakeup ISR overhead; 1/16 bit-time noise detection; DMA transmission for both transmit and receive - SPI -- Two serial peripheral interfaces with full-duplex or single-wire bidirectional option; double-buffered transmitter and receiver; master or slave mode operation; selectable MSB-first or LSB-first shifting; 8-bit or 16-bit data modes; programmable transmit bit rate; receive data buffer hardware match feature; DMA transmission for transmit and receive * Input/Output - Up to 69 GPIOs and one Input-only pin - Interrupt or DMA request with selectable polarity on all input pins - Programmable glitch filter, hysteresis and configurable pull up/down device on all input pins - Configurable slew rate and drive strength on all output pins - Independent pin value register to read logic level on digital pin - Up to 16 rapid general purpose I/O (RGPIO) pins connected to the processor's local 32-bit platform bus with set, clear, and faster toggle functionality MCF51AG128 ColdFire Microcontroller, Rev. 5 2 Freescale Semiconductor Table of Contents 1 MCF51AG128 Family Configurations . . . . . . . . . . . . . . . . . . . .4 1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .14 2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .14 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15 2.4 Electrostatic Discharge (ESD) Protection Characteristics 16 2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21 2.7 High Speed Comparator (HSCMP) Electricals . . . . . . .23 2.8 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .23 2.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.10 External Oscillator (XOSC) Characteristics . . . . . . . . .27 2.11 ICS Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.12.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . .31 2.12.3 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . .32 2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .35 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .37 5.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .37 5.2 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .40 5.3 64-pin QFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.4 48-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .46 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 17 Table 10. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 21 Table 11.HSCMP Electrical Specifications. . . . . . . . . . . . . . . . . 23 Table 12.5V 12-bit ADC Operating Conditions. . . . . . . . . . . . . . 23 Table 13.5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14.Oscillator Electrical Specifications (Temperature Range = -40 to 105 C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15.ICS Frequency Specifications (Temperature Range = -40 to 105 C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17.TPM/FTM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18.SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . 32 Table 19.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 20.Orderable Part Number Summary. . . . . . . . . . . . . . . . 36 Table 21.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 22.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2 List of Figures Figure 1. MCF51AG128 Series MCUs Block Diagram . . . . . . . . . 6 Figure 2. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. 64-Pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Typical IOH vs. VDD - VOH (Low Drive,PTxDSn = 0) . . 19 Figure 6. Typical IOH vs. VDD - VOH (High Drive, PTxDSn = 1) . 19 Figure 7. Typical IOL vs. VOL (Low Drive, PTxDSn = 0) . . . . . . . 20 Figure 8. Typical IOL vs. VOL (High Drive, PTxDSn = 1) . . . . . . . 20 Figure 9. Run Current at Different Conditions. . . . . . . . . . . . . . . 22 Figure 10.ADC Input Impedance Equivalency Diagram. . . . . . . 25 Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . 31 Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 33 Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 33 Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 34 Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 34 3 4 5 6 List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 9. MCF51AG128 Series Device Comparison. . . . . . . . . . .4 MCF51AG128 Series Functional Units . . . . . . . . . . . . . .7 Pin Availability by Package Pin-Count. . . . . . . . . . . . . .12 Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .14 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .16 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 MCF51AG128 ColdFire Microcontroller, Rev. 5 3 Freescale Semiconductor MCF51AG128 Family Configurations 1 1.1 MCF51AG128 Family Configurations Device Comparison The following table compares the various device derivatives available within the MCF51AG128 series MCUs. Table 1. MCF51AG128 Series Device Comparison MCF51AG128 Feature 80-pin Flash memory size (KB) RAM size (KB) ColdFire V1 core with BDM (background debug module) HSCMP (analog comparator) ADC (analog-to-digital converter) channels (12-bit) CRC (cyclic redundancy check) DAC DMA controller iEvent (intelligent Event module) EWM (External Watchdog Monitor) WDOG (Watchdog timer) RTC DBG (debug module) IIC (inter-integrated circuit) IRQ (interrupt request input) INTC (interrupt controller) LVD (low-voltage detector) ICS (internal clock source) OSC (crystal oscillator) Port I/O1 RGPIO (rapid general-purpose I/O) SCI (serial communications interface) SPI1 (serial peripheral interface) SPI2 (serial peripheral interface) FTM1 (flexible timer module) channels FTM2 channels Yes No No 62 62 69 16 53 16 39 15 2 Yes Yes No No 1 1 No Yes Yes Yes Yes Yes 69 16 53 16 39 15 2 2 1 4-ch Yes Yes Yes Yes Yes 1 1 No 2 24 2 19 1 12 Yes 2 2 1 64-pin 128 16 Yes 2 24 2 19 1 12 48-pin 80-pin 64-pin 96 48-pin MCF51AG96 MCF51AG128 ColdFire Microcontroller, Rev. 5 4 Freescale Semiconductor MCF51AG128 Family Configurations Table 1. MCF51AG128 Series Device Comparison (continued) MCF51AG128 Feature 80-pin TPM3 (timer pulse-width modulator) channels Debug Visibility Bus 1 2 MCF51AG96 48-pin 2 80-pin 64-pin 48-pin 64-pin Yes No No Yes No No Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module. Some pins of FTMx might not be bonded on small package, therefore these channels could be used as soft timer only. 1.2 Block Diagram Figure 1 shows the connections between the MCF51AG128 series pins and modules. MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 5 MCF51AG128 Family Configurations DBG BKGD/MS BDM BKPT RESET FTM1* SIM FTM2CLK SCI2 IRQ/ TPMCLK Port C: RXD2 TXD2 Port C ColdFire V1 core + DMA + iEvent FTM1CLK Port F: FTM1CH5 FTM1CH4 FTM1CH3 FTM1CH2 Port E: FTM1CH1 FTM1CH0 Port J: FTM2CH5 FTM2CH4 FTM2CH3 FTM2CH2 Port F: FTM2CH1 FTM2CH0 SCI1 Port E: RXD1 TXD1 Port B Port J: DDATA3DDATA0 PST3VBUS PST0 Port G: PSTCLK ADC Port B: ADP18ADP11 Port H: ADP22ADP19 Port A: ADP23 Port A: CMP2OUT CIN1 HSCMP2 C2IN2 C2IN3 Port A VREFH VREFL VDDA VSSA VREFH VREFL VDDA VSSA Port C,D,G: ADP10ADP0 Port D: CMP1OUT CIN1 C1IN2 HSCMP1 C1IN3 PTA7/ADP23 PTA6/MCLK PTA5/C2IN3 PTA4/C2IN2 PTA3/CMP2OUT PTA2/CIN1 PTA1/EWM_out PTA0/EWM_in PTB7/ADP11 PTB6/ADP12 PTB5/ADP13 PTB4/ADP14 PTB3/ADP15 PTB2ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTC6/FTM2FLT PTC5/RxD2 PTC4/SS2 PTC3/TxD2 PTC2/ADP8 PTC1/SDA PTC0/SCL PTD7/ADP7 PTD6/FTM1CLK/ADP0 PTD5/ADP1 PTD4/FTM2CLK/ADP2 PTD3/ADP5 PTD2/ADP6/CMP1OUT PTD1/ADP9/C1IN3 PTD0/ADP10/C1IN2 PTE7/RGPIO7/SPSCK1 PTE6/RGPIO6/MOSI1 PTE5/RGPIO5/MISO1 PTE4/RGPIO4/SS1 PTE3/RGPIO3/FTM1CH1 PTE2/RGPIO2/FTM1CH0 PTE1/RGPIO1/RxD1 PTE0/RGPIO0/TxD1 PTF7/RGPIO15 PTF6/RGPIO14/FTM1FLT PTF5/RGPIO13/FTM2CH1 PTF4/RGPIO12/FTM2CH0 PTF3/RGPIO11/FTM1CH5 PTF2/RGPIO10/FTM1CH4 PTF1/RGPIO9/FTM1CH3 PTF0/RGPIO8/FTM1CH2 PTG6/XTAL PTG5/EXTAL PTG4/ADP3 PTG3/ADP4 PTG2/BKPT PTG1/PSTCLK1/TPM3CH1 PTG0/PSTCLK0/TPM3CH0 PTH6/MISO2 PTH5/MOSI2 PTH4/SPSCK2 PTH3/ADP19/FTM2CH5 PTH2/ADP20/FTM2CH4 PTH1/ADP21/FTM2CH3 PTH0/ADP22/FTM2CH2 PTJ7/DDATA3/FTM2CH2 PTJ6/DDATA2/FTM2CH3 PTJ5/DDATA1/FTM2CH4 PTJ4/DDATA0//FTM2CH5 PTJ3/PST3 PTJ2/PST2 PTJ1/PST1 PTJ0/PST0 WDOG LVD IRQ FTM2 * SPI1 Port E: SS1 SPSCK1 MOSI1 MISO1 FLASH 128 or 96 KB TPMCLK RAM 16 KB Port F: RGPIO15 RGPIO14 RGPIO13 RGPIO12 RGPIO11 RGPIO10 RGPIO9 RGPIO8 TPM3 Port B: or Port G: TPM3CH1 TPM3CH0 Port H: SS2 SPI2 SPSCK2 MOSI2 MISO2 RGPIO Port E: RGPIO7 RGPIO6 RGPIO5 RGPIO4 RGPIO3 RGPIO2 RGPIO1 RGPIO0 CRC ICS RTC OSC Port G: EXTAL XTAL VDD VSS VSS DAC1 VREG DAC2 EWM IIC Port C: SDA SCL EWM_in EWM_out Figure 1. MCF51AG128 Series MCUs Block Diagram MCF51AG128 ColdFire Microcontroller, Rev. 5 6 Freescale Semiconductor Port J Port H Port G Port F Port E Port D MCF51AG128 Family Configurations 1.3 Features Table 2 describes the functional units of the MCF51AG128 series. Table 2. MCF51AG128 Series Functional Units Functional Unit CF1Core (V1 ColdFire core) BDM (background debug module) DBG (debug) VBUS (debug visibility bus) SIM (system integration module) Flash (flash memory) RAM (random-access memory) Function Executes programs and interrupt handlers Provides single pin debugging interface (part of the V1 ColdFire core) Provides debugging and emulation capabilities (part of the V1 ColdFire core) Allows for real-time program traces (part of the V1 ColdFire core) Controls resets and chip level interfaces between modules Provides storage for program code, constants, and variables Provides storage for program variables RGPIO (rapid general-purpose input/output) Allows for I/O port access at CPU clock speeds VREG (voltage regulator) LVD (low-voltage detect) CF1_INTC (interrupt controller) ADC (analog-to-digital converter) FTM1, FTM2 (flexible timer/pulse-width modulators) TPM3 (timer/pulse-width modulator) CRC (cyclic redundancy check) HSCMP1, HSCMP2 (analog comparators) DAC1, DAC2 (digital-to-analog converter) IIC (inter-integrated circuit) ICS (internal clock source) OSC (crystal oscillator) SCI1, SCI2 (serial communications interfaces) SPI1, SPI2 (8/16-bit serial peripheral interfaces) DMA iEvent EWM (External Watchdog Monitor) Controls power management across the device Monitors internal and external supply voltage levels, and generates a reset or interrupt when the voltages are too low Controls and prioritizes all device interrupts Measures analog voltages at up to 12 bits of resolution Provide a variety of timing-based features Provides a variety of timing-based features Accelerates computation of CRC values for ranges of memory Compare two analog inputs Provide programmable voltage reference for HSCMPx Supports standard IIC communications protocol Provides clocking options for the device, including a frequency-locked loop (FLL) for multiplying slower reference clock sources Allows a crystal or ceramic resonator to be used as the system clock source or reference clock for the FLL Serial communications UARTs capable of supporting RS-232 and LIN protocols Provide 8/16-bit 4-pin synchronous serial interface Provides the means to directly transfer data between system memory and I/O peripherals Highly programmable module for creating combinational boolean outputs for use as interrupt requests, DMA transfer requests, or hardware triggers Additional watchdog system to help reset external circuits MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 7 MCF51AG128 Family Configurations Table 2. MCF51AG128 Series Functional Units (continued) Functional Unit WDOG (Watchdog timer) RTC (Real Time Counter) Function keeps a watch on the system functioning and resets it in case of its failure Provides a constant time-base with optional interrupt MCF51AG128 ColdFire Microcontroller, Rev. 5 8 Freescale Semiconductor MCF51AG128 Family Configurations 1.4 Pin Assignments This section describes the pin assignments for the available packages. Figure 2 shows the pinout of the 80-pin LQFP. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PTC5/RxD2 PTC3/TxD2 PTH6/MISO2 PTH5/MOSI2 PTH4/SPCK2 RESET BKGD/MS PTG6/XTAL PTG5/EXTAL VSS VDD VDDA VREFH VREFL VSSA PTC4/SS2 PTD6/FTM1CLK/ADP0 PTD5/ADP1 PTD4/FTM2CLK/ADP2 PTG4/ADP3 PTE4/RGPIO4/SS1 PTE5/RGPIO5/MISO1 PTE6/RGPIO6/MOSI1 PTE7/RGPIO7/SPSCK1 PTJ4/DDATA0/FTM2CH5 PTJ5/DDATA1/FTM2CH4 PTJ6/DDATA2/FTM2CH3 PTJ7/DDATA3/FTM2CH2 PTG0/PSTCLK0/TPM3CH0 VSS VDD PTG1/PSTCLK1/TPM3CH1 PTG2/BKPT PTA0/EWM_in PTA1/EWM_out PTA2/CIN1 PTA3/CMP2OUT PTA4/C2IN2 PTA5/C2IN3 PTA6/MCLK 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PTC0/SCL PTC1/SDA IRQ/TPMCLK PTF0/RGPIO8/FTM1CH2 PTF1/RGPIO9/FTM1CH3 PTF2/RGPIO10/FTM1CH4 PTF3/RGPIO11/FTM1CH5 PTF4/RGPIO12/FTM2CH0 PTC6/FTM2FLT PTF7/RGPIO15 PTF5/RGPIO13/FTM2CH1 PTF6/RGPIO14/FTM1FLT PTJ0/PST0 PTJ1/PST1 PTJ2/PST2 PTJ3/PST3 PTE0/RGPIO0/TxD1 PTE1/RGPIO1/RxD1 PTE2/RGPIO2/FTM1CH0 PTE3/RGPIO3/FTM1CH1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80-Pin LQFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTG3/ADP4 PTD3/ADP5 PTD2/ADP6/CMP1OUT PTD7/ADP7 PTC2/ADP8 PTD1/ADP9/C1IN3 PTD0/ADP10/C1IN2 PTB7/ADP11 PTB6/ADP12 PTB5/ADP13 PTB4/ADP14 PTB3/ADP15 PTB2/ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTH3/ADP19/FTM2CH5 PTH2/ADP20/FTM2CH4 PTH1/ADP21/FTM2CH3 PTH0/ADP22/FTM2CH2 PTA7/ADP23 Note: Pin names in bold are not available in lower pin count packages. Figure 2. 80-Pin LQFP MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 9 MCF51AG128 Family Configurations Figure 3 shows the pinout of the 64-pin LQFP and QFP. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTC0/SCL PTC1/SDA IRQ/TPMCLK PTF0/RGPIO8/FTM1CH2 PTF1/RGPIO9/FTM1CH3 PTF2/RGPIO10/FTM1CH4 PTF3/RGPIO11/FTM1CH5 PTF4/RGPIO12/FTM2CH0 PTC6/FTM2FLT PTF7/RGPIO15 PTF5/RGPIO13/FTM2CH1 PTF6/RGPIO14/FTM1FLT PTE0/RGPIO0/TxD1 PTE1/RGPIO1/RxD1 PTE2/RGPIO2/FTM1CH0 PTE3/RGPIO3/FTM1CH1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTC5/RxD2 PTC3/TxD2 PTH5 RESET BKGD/MS PTG6/XTAL PTG5/EXTAL VSS VDD VDDA VREFH VREFL VSSA PTD6/FTM1CLK/ADP0 PTD5/ADP1 PTD4/FTM2CLK/ADP2 64-Pin QFP 64-Pin LQFP PTG3/ADP4 PTD3/ADP5 PTD2/ADP6/CMP1OUT PTD7/ADP7 PTC2/ADP8 PTD1/ADP9/C1IN3 PTD0/ADP10/C1IN2 PTB7/ADP11 PTB6/ADP12 PTB5/ADP13 PTB4/ADP14 PTB3/ADP15 PTB2/ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTA7/ADP23 10 PTE4/RGPIO4/SS1 PTE5/RGPIO5/MISO1 PTE6/RGPIO6/MOSI1 PTE7/RGPIO7/SPSCK1 PTJ6/FTM2CH3 PTJ7/FTM2CH2 PTG0/TPM3CH0 VSS VDD PTA0/EWM_in PTA1/EWM_out PTA2/CIN1 PTA3/CMP2OUT PTA4/C2IN2 PTA5/C2IN3 PTA6/MCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. 64-Pin QFP and LQFP MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor MCF51AG128 Family Configurations Figure 4 shows the pinout of the 48-pin LQFP. PTC5/RXD2 PTC3/TXD2 PTH5 RESET BKGD/MS PTG6/XTAL PTG5/EXTAL VSS VDD VDDAD / VREFH VSSAD / VREFL PTD6/FTM1CLK/ADP0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 IRQ/TPMCLK PTF0/RGPIO8/FTM1CH2 PTF1/RGPIO9/FTM1CH3 PTF2/RGPIO10/FTM1CH4 PTF3/RGPIO11/FTM1CH5 PTF4/RGPIO12/FTM2CH0 PTC6/FTM2FLT PTF7/RGPIO15 PTF5/RGPIO13/FTM2CH1 PTF6/RGPIO14/FTM1FLT PTE0/RGPIO0/TXD1 PTE1/RGPIO1/RXD1 1 2 3 4 5 6 7 8 9 10 11 48 LQFP MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 11 PTE2 /RGPIO2/FTM1CH0 PTE4/RGPIO4 / SS1 PTE5 /RGPIO5/MISO1 PTE6 /RGPIO6/ MOSI1 Figure 4. 48-Pin LQFP PTE7 /RGPIO7/ SPSCK1 PTJ6/FTM2CH3 PTJ7/FTM2CH2 PTG0/TPM3CH0 VSS VDD PTA0/EWM_in PTA1/EWM_out 13 14 15 16 17 18 19 20 21 22 23 24 12 PTD2/ADP6/CMP1OUT PTD1/ADP9/CMP1IN3 PTD0/ADP10/CMP1IN2 PTB7/ADP11 PTB6/ADP12 PTB5/ADP13 PTB4/ADP14 PTB3/ADP15 PTB2/ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTA3 MCF51AG128 Family Configurations Table 3 shows the package pin assignments. Table 3. Pin Availability by Package Pin-Count Pin Number 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 1 2 3 4 5 6 7 8 9 10 11 12 -- -- -- -- 13 14 15 16 17 18 19 20 -- -- 21 22 23 24 25 -- -- 26 27 28 29 30 31 32 48 -- -- 1 2 3 4 5 6 7 8 9 10 -- -- -- -- 11 12 13 -- 14 15 16 17 -- -- 18 19 20 21 22 -- -- 23 24 -- 25 -- -- -- Lowest <-Port Pin PTC0 PTC1 IRQ PTF0 PTF1 PTF2 PTF3 PTF4 PTC6 PTF7 PTF5 PTF6 PTJ0 PTJ1 PTJ2 PTJ3 PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 PTE6 PTE7 PTJ4 PTJ5 PTJ6 PTJ7 PTG0 VSS VDD PTG1 PTG2 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PSTCLK1 BKPT EWM_in EWM_out CIN1 CMP2OUT C2IN2 C2IN3 MCLK TPM3CH1 SCL SDA TPMCLK1 RGPIO8 RGPIO9 RGPIO10 RGPIO11 RGPIO12 FTM2FLT RGPIO15 RGPIO13 RGPIO14 PST0 PST1 PST2 PST3 RGPIO0 RGPIO1 RGPIO2 RGPIO3 RGPIO4 RGPIO5 RGPIO6 RGPIO7 DDATA0 DDATA1 DDATA2 DDATA3 PSTCLK0 TxD1 RxD1 FTM1CH0 FTM1CH1 SS1 MISO1 MOSI1 SPSCK1 FTM2CH5 FTM2CH4 FTM2CH3 FTM2CH2 TPM3CH0 FTM2CH1 FTM1FLT FTM1CH2 FTM1CH3 FTM1CH4 FTM1CH5 FTM2CH0 Priority Alt 1 --> Highest Alt 2 MCF51AG128 ColdFire Microcontroller, Rev. 5 12 Freescale Semiconductor MCF51AG128 Family Configurations Table 3. Pin Availability by Package Pin-Count (continued) Pin Number 80 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 33 -- -- -- -- 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 -- 49 50 51 -- 52 53 54 55 56 57 58 59 60 61 -- 62 -- 63 64 48 -- -- -- -- -- 26 27 28 29 30 31 32 33 34 35 -- -- 36 -- -- -- -- -- 37 -- 38 38 39 39 40 41 42 43 44 45 -- 46 -- 47 48 Lowest <-Port Pin PTA7 PTH0 PTH1 PTH2 PTH3 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTD0 PTD1 PTC2 PTD7 PTD2 PTD3 PTG3 PTG4 PTD4 PTD5 PTD6 PTC4 VSSA VREFL VREFH VDDA VDD VSS PTG5 PTG6 BKGD RESET PTH4 PTH5 PTH6 PTC3 PTC5 SPSCK2 MOSI2 MISO2 TxD2 RxD2 EXTAL XTAL MS Priority Alt 1 ADP23 ADP22 ADP21 ADP20 ADP19 ADP18 ADP17 ADP16 ADP15 ADP14 ADP13 ADP12 ADP11 ADP10 ADP9 ADP8 ADP7 ADP6 ADP5 ADP4 ADP3 FTM2CLK ADP1 FTM1CLK SS2 ADP0 ADP2 CMP1OUT C1IN2 C1IN3 FTM2CH2 FTM2CH3 FTM2CH4 FTM2CH5 TPM3CH0 TPM3CH1 --> Highest Alt 2 MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 13 Preliminary Electrical Characteristics 1 TPMCLK, FTM1CLK, and FTM2CLK options are configured via software; out of reset, FTM1CLK, FTM2CLK, and TPMCLK are available to FTM1, FTM2, and TPM3 respectively. 2 Preliminary Electrical Characteristics This section contains electrical specification tables and reference timing diagrams for the MCF51AG128 series MCUs, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this data sheet supersede any values found in the module specifications. 2.1 Parameter Classification Table 4. Parameter Classifications P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: T D NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. 2.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 5 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). MCF51AG128 ColdFire Microcontroller, Rev. 5 14 Freescale Semiconductor Preliminary Electrical Characteristics Table 5. Absolute Maximum Ratings Rating Supply voltage Input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Maximum current into VDD Storage temperature 1 Symbol VDD VIn ID IDD Tstg Value -0.3 to 5.8 -0.3 to VDD + 0.3 25 120 -55 to 150 Unit V V mA mA C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. 2.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD is very small. Table 6. Thermal Characteristics Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance 1,2,3,4 80-pin LQFP 1s 2s2p 64-pin QFP 1s 2s2p 64-pin LQFP 1s 2s2p 48-pin LQFP 1s 2s2p 69 51 67 49 JA 54 41 C/W 56 45 Symbol TA TJ Value -40 to 105 150 Unit C C MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 15 Preliminary Electrical Characteristics 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection 3 1s -- Single layer board, one signal layer 4 2s2p -- Four layer board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA) where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273 C) Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3 Eqn. 2 Eqn. 1 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 2.4 Electrostatic Discharge (ESD) Protection Characteristics Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E. A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 7. ESD and Latch-up Test Conditions Model Human Body Series Resistance Storage Capacitance Number of Pulse per pin Description Symbol R1 C -- Value 1500 100 3 Unit pF -- MCF51AG128 ColdFire Microcontroller, Rev. 5 16 Freescale Semiconductor Preliminary Electrical Characteristics Table 7. ESD and Latch-up Test Conditions (continued) Model Latch-up Description Minimum input voltage limit Maximum input voltage limit Symbol -- -- Value -2.5 7.5 Unit V V Table 8. ESD and Latch-Up Protection Characteristics Num 1 2 3 Rating Human Body Model (HBM) Charge Device Model (CDM) Latch-up Current at TA = 85C Symbol VHBM VCDM ILAT Min 2000 500 100 Max -- -- -- Unit V V mA 2.5 DC Characteristics Table 9. DC Characteristics Num C 1 -- Operating voltage Output high voltage -- Low Drive (PTxDSn = 0) 5 V, ILoad = -5 mA 3 V, ILoad = -1.5 mA 5V, ILoad = -3 mA, PTC0 and PTC1 3V, ILoad = -1.5 mA, PTC0 and PTC1 Output high voltage -- High Drive (PTxDSn = 1) 5 V, ILoad = -20 mA P 3 V, ILoad = -8 mA 5V, ILoad = -12 mA, PTC0 and PTC1 3V, ILoad = -8 mA, PTC0 and PTC1 Output low voltage -- Low Drive (PTxDSn = 0) 5 V, ILoad = 5 mA 3 V, ILoad = 1.5 mA 5V, ILoad = 3 mA, PTC0 and PTC1 3V, ILoad = 1.5 mA, PTC0 and PTC1 Output low voltage -- High Drive (PTxDSn = 1) 5 V, ILoad = 20 mA P 3 V, ILoad = 8 mA 5V, ILoad = 12 mA, PTC0 and PTC1 3V, ILoad = 8 mA, PTC0 and PTC1 C Output high current -- Max total IOH for all ports 5V 3V Output low current -- Max total IOL for all ports 5V 3V Parameter Symbol Min 2.7 VDD - 1.5 VDD - 0.8 VDD - 0.4 VDD - 0.4 VDD - 1.5 VDD - 0.8 VDD - 0.4 VDD - 0.4 -- -- -- -- -- -- -- -- IOHT -- -- -- -- Typical1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 5.5 -- -- -- -- -- -- -- -- 1.5 0.8 0.4 0.4 1.5 0.8 0.4 0.4 100 60 100 60 Unit V This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. VOH 2 V VOL 3 V 4 mA 5 C IOLT mA MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 17 Preliminary Electrical Characteristics Table 9. DC Characteristics (continued) Num C 6 7 8 9 10 11 12 13 14 15 Parameter Symbol VIH VIL Vhys |IIn| 2 Min 0.65 x VDD -- 0.06 x VDD -- -- 20 10 20 -- 0.9 10 Typical1 -- -- -- 0.1 0.1 45 22 45 -- 1.4 -- Max -- 0.35 x VDD -- 1 1 65 32 65 8 2.0 -- Unit V mV A A k k pF V s P Input high voltage; all digital inputs P Input low voltage; all digital inputs D Input hysteresis; all digital inputs P Input leakage current; input only pins2 P High Impedance (off-state) leakage current P Internal pullup resistors Internal pullup resistorsPTC0 and PTC1 3 |IOZ| RPU RPD CIn VPOR tPOR VLVD1 P Internal pulldown resistors4 C Input Capacitance; all non-supply pins P POR rearm voltage D POR rearm time Low-voltage detection threshold -- high range VDD falling VDD rising Low-voltage detection threshold -- low range VDD falling VDD rising Low-voltage warning threshold -- high range 1 VDD falling VDD rising Low-voltage warning threshold -- high range 0 VDD falling VDD rising Low-voltage warning threshold low range 1 VDD falling VDD rising Low-voltage warning threshold -- low range 0 VDD falling VDD rising Low-voltage inhibit reset/recover hysteresis 5V 3V RAM retention voltage DC injection current5 6 7 8 (single pin limit) VIN >VDD VIN P 3.9 4.0 4.0 4.1 4.1 4.2 V 17 P VLVD0 2.48 2.54 2.56 2.62 2.64 2.70 V 18 P VLVW3 4.5 4.6 4.6 4.7 4.7 4.8 V 19 P VLVW2 4.2 4.3 4.3 4.4 4.4 4.5 V 20 P VLVW1 2.84 2.90 2.92 2.98 3.00 3.06 V 21 P VLVW0 2.66 2.72 -- -- -- 2.74 2.80 100 60 0.6 2.82 2.88 -- -- 1.0 V 22 T Vhys VRAM mV 23 D V 0 0 IIC 0 0 -- -- 2 -0.2 mA 24 D DC injection current (Total MCU limit, includes sum of all stressed pins) VIN >VDD VIN 25 -5 mA MCF51AG128 ColdFire Microcontroller, Rev. 5 18 Freescale Semiconductor Preliminary Electrical Characteristics 1 2 3 4 5 6 7 8 Typical values are based on characterization data at 25C unless otherwise stated. Measured with VIn = VDD or VSS. Measured with VIn = VSS. Measured with VIn = VDD. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. The RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD. Typical VDD - VOH vs. IOH A VDD = 5V T 1.4 1.2 Typical VDD - VOH vs. IOH AT VDD=3V 0.8 Hot (105C) Room (25C) Cold (-40C) Hot (105C) Room (25C) Cold (-40C) 0.8 0.6 0.4 0.2 0.0 0 -1 -2 -3 -4 -5 VDD - VOH (v) VDD - VOH (v) 1.0 0.6 0.4 0.2 0.0 0 -1 -2 IOH (mA) IOH (mA) Figure 5. Typical IOH vs. VDD - VOH (Low Drive,PTxDSn = 0) Typical VDD - VOH vs. IOH AT VDD = 5V 1.4 1.2 1.0 VDD - VOH (v) 0.8 0.6 0.4 0.2 0.0 Hot (105C) Room (25C) Cold (-40C) 0.6 0.8 Typical VDD - VOH vs. IOH AT VDD=3V Hot (105C) Room (25C) Cold (-40C) VDD - VOH (v) 0.4 0.2 0.0 0 -1 -2 -3 -4 -5 -6 -7 -8 0 -1 -2 -3 -4 -5 -6 -7 -8 -1 9 -10 1 -1 -12 3 -1 -14 5 -1 -16 -17 8 -1 -29 0 IOH (mA) IOH (mA) Figure 6. Typical IOH vs. VDD - VOH (High Drive, PTxDSn = 1) MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 19 Preliminary Electrical Characteristics Typical VOL vs. IOL AT VDD = 5V 1.40 1.20 1.00 Hot (105C) Room (25C) Cold (-40C) 0.60 0.80 Typical VOL vs. IOL AT VDD = 3V Hot (105C) Room (25C) Cold (-40C) 0.40 VOL (v) 0.80 0.60 0.40 0.20 VOL (v) 0.20 0.00 0.00 0 1 2 3 4 5 0 1 2 IOL (mA) IOL (mA) Figure 7. Typical IOL vs. VOL (Low Drive, PTxDSn = 0) Typical VOL vs. IOL AT VDD = 5V 1.40 1.20 1.00 Hot (105C) Room (25C) Cold (-40C) Typical VOL vs. IOL AT VDD = 3V 0.80 Hot (105C) 0.60 Room (25C) Cold (-40C) 0.40 VOL (v) 0.60 0.40 0.20 0.00 VOL (v) 0.80 0.20 0.00 0 0 2 4 6 8 16 12 10 14 20 18 1 2 3 4 5 6 7 8 IOL (mA) IOL (mA) Figure 8. Typical IOL vs. VOL (High Drive, PTxDSn = 1) MCF51AG128 ColdFire Microcontroller, Rev. 5 20 Freescale Semiconductor Preliminary Electrical Characteristics 2.6 Num 1 Supply Current Characteristics Table 10. Supply Current Characteristics C C Parameter Run supply current3 measured at 4 MHz CPU clock (All Peripheral Clocks are ON) Run supply current3 measured at 16 MHz CPU clock (All Peripheral Clocks are ON) Run supply current3 measured at 32 MHz CPU clock (All Peripheral Clocks are ON) Run supply current measured at 50MHz CPU clock (All Peripheral Clocks are ON) Run supply current3 measured at 4 MHz CPU clock (All Peripheral Clocks are OFF4) Run supply current3 measured at 16 MHz CPU clock (All Peripheral Clocks are OFF4) Run supply current3 measured at 32 MHz CPU clock (All Peripheral Clocks are OFF4) 50 MHz CPU Run supply current clock (All Peripheral Clocks are OFF4) Wait supply current3 measured at 4 MHz CPU clock Wait supply current3 measured at 16 MHz CPU clock Wait supply current3 measured at 32 MHz CPU clock Wait supply current3 measured at 50 MHz CPU clock Stop2 mode supply current -40 C 25 C 105 C -40 C 25 C 105 C S2IDD WIDD 3 measured at 3 Symbol RIDD VDD (V) 5 3 5 3 5 3 5 3 Typical1 5.8 5.7 21 20.9 39.2 39.1 57.9 57.8 4.7 4.6 16.1 15.9 29 28.9 44.1 44.0 3.2 3.2 10.1 10 19 18.8 29.2 29 1.17 1.35 28.6 1.0 1.34 26.8 Max2 7 7 25 25 50 50 70 70 6 6 20 20 35 35 50 50 5 5 13 13 25 25 40 40 3 3 40 3 3 40 Unit mA 2 C mA mA 3 C 4 P mA 5 C RIDD 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 mA 6 C mA mA 7 C 8 C mA 9 C mA 10 C mA 11 C mA 12 C mA 13 C P C C P C A 3 A MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 21 Preliminary Electrical Characteristics Table 10. Supply Current Characteristics Num 14 C P C C P C 15 C P C C P C 16 C C Parameter Stop3 mode supply current -40 C 25 C 105 C -40 C 25 C 105 C Stop4 mode supply current -40 C 25 C 105 C -40 C 25 C 105 C RTC adder to stop2 or stop35, 25 C S23IDDRTC S4IDD Symbol S3IDD VDD (V) 5 Typical1 1.2 1.7 43.3 1.04 1.6 45.5 Max2 3 3 60 3 3 60 Unit A 3 A 5 106 109 155 95 98 142 300 300 5 130 130 170 130 130 170 -- -- -- A 3 A 5 3 nA nA A 17 1 2 3 4 5 6 C Adder to stop3 for oscillator enabled (ERCLKEN = 1 and EREFSTEN = 1) 6 S3IDDOSC 5, 3 Typicals are measured at 25 C. Values given here are preliminary estimates prior to completing characterization. Code run from flash, FEI mode, and does not include any dc loads on port pins. Bus CLK= (CPU CLK/2) GPIO filters are working on LPO clock. Most customers are expected to use auto-wakeup from stop2 or stop3 instead of the higher current wait mode. Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0). Figure 9. Run Current at Different Conditions MCF51AG128 ColdFire Microcontroller, Rev. 5 22 Freescale Semiconductor Preliminary Electrical Characteristics 2.7 Num 1 2 3 High Speed Comparator (HSCMP) Electricals Table 11. HSCMP Electrical Specifications C -- T T Supply voltage Supply current, high speed mode (EN = 1, PMODE = 1) Supply current, low speed mode (EN = 1, PMODE = 0) Analog input voltage Analog input offset voltage Analog Comparator hysteresis Propagation delay, high speed mode (EN = 1, PMODE = 1) Propagation delay, low speed mode (EN = 1, PMODE = 0) Analog Comparator initialization delay Rating Symbol VDD IDDAHS IDDALS Min 2.7 -- -- Typical -- 200 20 Max 5.5 -- -- Unit V A A 4 5 6 7 8 9 -- D D D D D VAIN VAIO VH tDHS tDLS tAINIT VSS - 0.3 -- 3.0 -- -- -- -- 5 9.0 70 400 400 VDD 40 20.0 120 600 -- V mV mV ns ns ns 2.8 Num 1 2 3 4 5 6 7 8 Digital to Analog (DAC) Characteristics C D D D D D D D P Supply voltage Supply current (enabled) Supply current (stand-by) DAC reference input voltage DAC setup delay DAC step size DAC output voltage range Bandgap voltage reference factory trimmed at VDD = 5 V, Temp = 25 C Rating Symbol VDDA IDDAC IDDACS Vin1,Vin2 tPRGST Vstep Vdacout VBG Min 2.7 -- -- VSSA -- 3Vin/128 Vin/32 1.18 Typical -- -- -- -- 1000 Vin/32 -- 1.20 Max 5.5 20 150 VDDA -- 5Vin/128 Vin 1.21 Unit V A nA V nS V V V 2.9 ADC Characteristics Table 12. 5V 12-bit ADC Operating Conditions Characterist ic Supply voltage Typic al1 -- 0 0 Num 1 C D Conditions Absolute Delta to VDD (VDD-VDDA)2 Delta to VSS (VSS-VSSA)2 Symb VDDA VDDA VSSA Min 2.7 -100 -100 Max 5.5 100 100 Unit V mV mV Comment -- -- -- 2 D Ground voltage MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 23 Preliminary Electrical Characteristics Table 12. 5V 12-bit ADC Operating Conditions (continued) Num 3 4 5 6 7 8 C D D D C C C Characterist ic Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance Input Resistance Analog Source Resistance Conditions -- -- -- -- -- 12 bit mode fADCK > 4 MHz fADCK < 4 MHz 10 bit mode fADCK > 4 MHz fADCK < 4 MHz 8 bit mode (all valid fADCK) ADC Conversion Clock Freq. High Speed (ADLPC = 0) Low Power (ADLPC = 1) fADCK Symb VREFH VREFL VADIN CADIN RADIN RAS -- -- -- -- -- 0.4 0.4 -- -- -- -- -- -- -- 2 5 5 10 10 8.0 4.0 MHz -- -- Min 2.7 VSSAD VREFL -- -- Typic al1 VDDA VSSA -- 4.5 3 Max VDDA VSSA VREFH 5.5 5 Unit V V V pF k k Comment -- -- -- -- -- External to MCU C C 9 D D 1 Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. MCF51AG128 ColdFire Microcontroller, Rev. 5 24 Freescale Semiconductor Preliminary Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS Pad leakage due to input protection ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + - CAS - RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure 10. ADC Input Impedance Equivalency Diagram Table 13. 5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Num 1 C T Characteristic Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply Current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply Current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply Current ADLPC = 0 ADLSMP = 0 ADCO = 1 Supply Current Conditions -- Symb IDDAD Min -- Typical1 181 Max -- Unit A Comment -- 2 T -- IDDAD -- 334 -- A -- 3 T -- IDDAD -- 385 -- A -- 4 D -- IDDAD -- 0.717 1 mA -- 5 T Stop, Reset, Module Off IDDAD -- 0.065 1 A -- MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 25 Preliminary Electrical Characteristics Table 13. 5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Num 6 C P Characteristic ADC Asynchronous Clock Source Conditions High Speed (ADLPC = 0) Low Power (ADLPC = 1) Short Sample (ADLSMP = 0) Long Sample (ADLSMP = 1) Short Sample (ADLSMP = 0) Long Sample (ADLSMP = 1) 9 T P T 10 T P T 11 T P T 12 T P T 13 T P T 14 D Quantization Error Full-Scale Error Zero-Scale Error Integral Non-Linearity Differential Non-Linearity Total Unadjusted Error 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode3 8 bit mode5 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode 8 bit mode 15 D Input Leakage Error 12 bit mode 10 bit mode 8 bit mode EIL EQ EFS EZS INL DNL ETUE tADS tADC Symb fADACK Min 2 1.25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typical1 3.3 2 20 40 3.5 23.5 3.0 1 0.5 1.75 0.5 0.3 1.5 0.5 0.3 1.5 0.5 0.5 1 0.5 0.5 -1 to 0 -- -- 1 0.2 0.1 Max 5 3.3 -- -- -- -- -- 2.5 1.0 -- 1.0 0.5 -- 1.0 0.5 -- 1.5 0.5 -- 1 0.5 -- 0.5 0.5 -- 2.5 1 LSB2 Pad leakage4 * RAS LSB2 -- LSB2 VADIN = VDDAD LSB2 VADIN = VSSAD LSB2 -- LSB2 -- LSB2 Includes quantization ADCK cycles ADCK cycles See Table 10 for conversion time variances Unit MHz Comment tADACK = 1/fADACK 7 P Conversion Time (Including sample time) 8 T Sample Time MCF51AG128 ColdFire Microcontroller, Rev. 5 26 Freescale Semiconductor Preliminary Electrical Characteristics Table 13. 5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Num 16 17 C D D Characteristic Temp Sensor Voltage Temp Sensor Slope Conditions 25 C -40 C -- 25 C 25 C -- 85 C Symb VTEMP25 m Min -- -- -- Typical1 1.396 3.266 3.638 Max -- -- -- Unit mV Comment -- -- mV/C Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals. 1 2.10 Num C External Oscillator (XOSC) Characteristics Table 14. Oscillator Electrical Specifications (Temperature Range = -40 to 105 C Ambient) Rating Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode 2 High range (RANGE = 1, HGO = 1) FBELP mode High range (RANGE = 1, HGO = 0) FBELP mode Symbol Min Typical1 Max Unit 1 C flo fhi fhi-hgo fhi-lp C1 C2 32 1 1 1 -- -- -- -- 38.4 16 16 8 kHz MHz MHz MHz 2 3 -- Load capacitors Feedback resistor -- Series resistor Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0) High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time 3 Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0)4 High range, high gain (RANGE = 1, HGO = 1)3 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode 2 FBE mode2 FBELP mode t t t See crystal or resonator manufacturer's recommendation. 10 1 -- -- -- -- -- -- 0 100 0 0 0 0 1500 2000 3 7 -- -- -- -- M Low range (32 kHz to 100 kHz) High range (1 MHz to 16 MHz) RF 4 -- RS -- -- -- 0 10 20 -- -- -- -- k CSTL-LP 5 T CSTL-HGO t CSTH-LP CSTH-HGO -- -- -- -- ms 6 T fextal 0.03125 0 0 50.33 50.33 50.33 MHz 1 Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value. MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 27 Preliminary Electrical Characteristics 2 When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. 4 4 MHz crystal MCU EXTAL XTAL RS RF C1 Crystal or Resonator C2 2.11 ICS Specifications Table 15. ICS Frequency Specifications (Temperature Range = -40 to 105 C Ambient) Num C 1 2 3 4 Rating Symbol fint_ft fint_ut tirefst fdco_ut Min -- 31.25 -- 16 32 48 Typical1 32.768 -- 60 -- -- -- 16.82 33.69 50.48 0.1 0.2 0.5 -1.0 0.5 Max -- 39.06 100 20 40 60 -- -- -- 0.2 0.4 2 1 Unit kHz kHz s MHz C Internal reference frequency - factory trimmed at VDD = 5 V and temperature = 25 C C Average internal reference frequency - untrimmed T Internal reference startup time C DCO output frequency 2 C range - untrimmed C P DCO output frequency2 P Reference =32768Hz and DMX32 = 1 P Low range (DRS = 00) Mid range (DRS = 01) High range (DRS = 10) Low range (DRS = 00) Mid range (DRS = 01) High range (DRS = 10) 5 fdco_DMX32 -- -- -- MHz 6 7 8 9 D Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) D Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) D Total deviation of trimmed DCO output frequency over full voltage and temperature range D Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 -70 C fdco_res_t fdco_res_t fdco_t fdco_t -- -- -- -- %fdco %fdco %fdco %fdco MCF51AG128 ColdFire Microcontroller, Rev. 5 28 Freescale Semiconductor Preliminary Electrical Characteristics Table 15. ICS Frequency Specifications (continued)(Temperature Range = -40 to 105 C Ambient) Num C 10 11 12 D FLL acquisition time 3 Rating Symbol tfll_acquire CJitter floc_low Min -- -- (3/5) x fint Typical1 -- 0.02 -- Max 1 0.2 -- Unit ms %fdco kHz D Long term Jitter of DCO output clock (averaged over 2ms interval) 4 D Loss of external clock minimum freq. (RANGE = 0) * ext. clock freq: above (3/5)fint, never reset * ext. clock freq: between (2/5)fint and (3/5)fint, maybe reset (phase dependency) * ext. clock freq: below (2/5)fint, always reset D Loss of external clock minimum freq. (RANGE = 1) * ext. clock freq: above (16/5)fint, never reset * ext. clock freq: between (15/5)fint and (16/5)fint, maybe reset (phase dependency) * ext. clock freq: below (15/5)fint, always reset 13 floc_high (16/5) x fint -- -- kHz Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f BUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry by VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 1 2 MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 29 Preliminary Electrical Characteristics 2.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. 2.12.1 Num 1 2 3 4 5 6 7 C D D D D D D D Control Timing Table 16. Control Timing Parameter Bus frequency (tcyc = 1/fBus) Internal low-power oscillator period External reset pulse width (tcyc = 1/fSelf_reset) Reset low drive Active background debug mode latch setup time Active background debug mode latch hold time IRQ pulse width Asynchronous path2 Synchronous path3 Port rise and fall time (load = 30 pF for SPI, rest 50 pF)4 Slew rate control disabled (PTxSE = 0) High drive Slew rate control enabled (PTxSE = 1) High drive Slew rate control disabled (PTxSE = 0) Low drive Slew rate control enabled (PTxSE = 1) Low drive tILIH, tIHIL 100 1.5 x tcyc -- -- ns 2 Symbol fBus tLPO textrst trstdrv tMSSU tMSH Min dc 800 100 66 x tcyc 500 100 Typ1 -- -- -- -- -- -- Max 24 1500 -- -- -- -- Unit MHz s ns ns ns ns 8 tRise, tFall -- -- 11 35 40 75 ns Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40C to 105C. 1 2 textrst RESET PIN Figure 11. Reset Timing MCF51AG128 ColdFire Microcontroller, Rev. 5 30 Freescale Semiconductor Preliminary Electrical Characteristics tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 12. IRQ/KBIPx Timing 2.12.2 Timer (TPM/FTM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 17. TPM/FTM Input Timing NUM 1 2 3 4 5 C -- -- D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTPMext tTPMext tclkh tclkl tICPW Min DC 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit MHz tcyc tcyc tcyc tcyc tTPMext tclkh TPMxCLK tclkl Figure 13. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure 14. Timer Input Capture Pulse MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 31 Preliminary Electrical Characteristics 2.12.3 SPI Characteristics Table 18 and Figure 15 through Figure 18 describe the timing requirements for the SPI system. Table 18. SPI Timing Characteristics No. -- C D Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid time ( maximum delay after SPCLK edge to Data output) Master Slave Data hold time ( minimum delay after SPCLK edge to Data output) Master Slave Symbol fop Min fBus/2048 0 2 4 1/2 1 1/2 1 tcyc - 30 tcyc - 30 30 30 10 10 -- -- Max fBus/2 fBus/4 2048 -- -- -- -- -- 1024 tcyc -- -- -- -- -- -- -- Unit Hz 1 D tSPSCK tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc 2 D tLead 3 D tLag 4 D tWSPSCK 5 D tSU 6 D tHI ta tdis 7 8 D D 9 D tV1 -- -- 25 70 ns ns 10 1 D tHO1 10 10 -- -- ns ns SPI Output Load = 30 pf MCF51AG128 ColdFire Microcontroller, Rev. 5 32 Freescale Semiconductor Preliminary Electrical Characteristics SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) MSB IN2 9 MOSI (OUTPUT) MSB OUT2 6 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 3 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 15. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT(2) MSB IN(2) 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 6 BIT 6 . . . 1 LSB IN 4 3 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 16. SPI Master Timing (CPHA = 1) MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 33 Preliminary Electrical Characteristics SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT) NOTE: 3 4 4 8 9 MSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 10 10 SEE NOTE SLAVE LSB OUT 1. Not defined but normally MSB of character just received Figure 17. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) 2 3 4 4 9 SLAVE 5 MSB IN MSB OUT 6 10 BIT 6 . . . 1 SLAVE LSB OUT 8 BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure 18. SPI Slave Timing (CPHA = 1) 2.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see MCF51AG128 Reference Manual. MCF51AG128 ColdFire Microcontroller, Rev. 5 34 Freescale Semiconductor Preliminary Electrical Characteristics Table 19. Flash Characteristics Num 1 2 3 4 5 6 7 8 9 C -- -- -- -- -- -- -- -- C Characteristic Supply voltage for program/erase Supply voltage for read operation Internal FCLK frequency2 Internal FCLK period (1/FCLK) Byte program time (random location)2 Byte program time (burst mode) Page erase time3 Mass erase time2 Program/erase endurance4 TL to TH = -40 C to 105 C T = 25 C Data retention5 tD_ret 2 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass Min 2.7 2.7 150 5 Typical1 Max 5.5 5.5 200 6.67 Unit V V kHz s tFcyc tFcyc tFcyc tFcyc cycles 9 4 4000 20,000 10,000 -- 15 -- 100,000 100 -- -- -- 10 1 2 C years Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. The frequency of this clock is controlled by a software setting. 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. 2.14 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 2.14.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 35 Ordering Information 3 Ordering Information MCF 51 AG 128 V XX Status (MCF = Fully Qualified ColdFire) (PCF = Product Engineering) Core Family Package designator Temperature range (V = -40 C to 105 C, C = -40C to 85 C ) Memory size designator This section contains ordering information for MCF51AG128 devices. Table 20. Orderable Part Number Summary Freescale Part Number MCF51AG128VLK MCF51AG128VLH MCF51AG128VQH MCF51AG128VLF MCF51AG96VLK MCF51AG96VLH MCF51AG96VQH MCF51AG96VLF Description MCF51AG128 ColdFire Microcontroller MCF51AG128 ColdFire Microcontroller MCF51AG128 ColdFire Microcontroller MCF51AG128 ColdFire Microcontroller MCF51AG96 ColdFire Microcontroller MCF51AG96 ColdFire Microcontroller MCF51AG96 ColdFire Microcontroller MCF51AG96 ColdFire Microcontroller Flash / SRAM (KB) 128 / 16 128 / 16 128 / 16 128 / 16 96 / 16 96 / 16 96 / 16 96 / 16 Package 80 LQFP 64 LQFP 64 QFP 48 LQFP 80 LQFP 64 LQFP 64 QFP 48 LQFP Temperature -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C -40C to 105C 4 80 64 64 48 Package Information Table 21. Package Descriptions Pin Count Package Type Low Quad Flat Package Low Quad Flat Package Quad Flat Package Low Quad Flat Package Abbreviation LQFP LQFP QFP LQFP Designator LK LH QH LF Case No. 917A 840F 840B 932 Document No. 98ASS23237W 98ASS23234W 98ASB42844B 98ASH00962A MCF51AG128 ColdFire Microcontroller, Rev. 5 36 Freescale Semiconductor Mechanical Outline Drawings 5 5.1 Mechanical Outline Drawings 80-pin LQFP Package MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 37 Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 38 Freescale Semiconductor Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 39 Mechanical Outline Drawings 5.2 64-pin LQFP Package MCF51AG128 ColdFire Microcontroller, Rev. 5 40 Freescale Semiconductor Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 41 Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 42 Freescale Semiconductor Mechanical Outline Drawings 5.3 64-pin QFP Package MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 43 Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 44 Freescale Semiconductor Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 45 Mechanical Outline Drawings 5.4 48-pin LQFP Package MCF51AG128 ColdFire Microcontroller, Rev. 5 46 Freescale Semiconductor Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 47 Revision History 6 Revision History Table 22. Revision History Rev. No. 1 2 3 4 Date 11/2008 4/2009 5/2009 12/2009 Initial Draft Release. Internal Release. Alpha Customer Release. * Added 48-pin LQFP information; * Updated Section 2.5/17 and 2.6/21. * Provided the supply current in Section 2.7/23, and setup delay in Section 2.8/23. * * * * * Updated Table 10. Added Figure 9. Corrected pin names of PTG6 and PTG5 in 48-pin LQFP. Standardized Generation 2008 Watchdog to Watchdog. In Table 9, updated Output high/low voltage -- Low Drive (PTxDSn = 0) 3 V, ILoad value. Description 5 6/2010 MCF51AG128 ColdFire Microcontroller, Rev. 5 48 Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 49 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2010. All rights reserved. Document Number: MCF51AG128 Rev. 5 6/2010 |
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